1. Field of the Invention
The present invention relates to stabilization of maximum amplitude values of signals outputted from a differential amplifier circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional differential amplifier circuit.
The present differential amplifier circuit comprises a bias unit 10 and an amplifying unit 20.
The bias unit 10 generates a bias voltage Vb for causing a constant current to flow into the amplifying unit 20 and has an operational amplifier (OP) 11 supplied with a reference voltage Vref from an unillustrated constant voltage unit. A − input terminal of the operational amplifier 11 is supplied with the reference voltage Vref and a + input terminal thereof is connected to a node N1. The node N1 is connected to a power supply or source potential VSS via a resistor 12 and connected to a power supply or source potential VDD via a P channel MOS transistor (hereinafter called “PMOS”) 13. The gate of the PMOS 13 is connected to an output terminal of the operational amplifier 11 and connected to the gate of a PMOS 14 that constitutes a current mirror circuit. The source and drain of the PMOS 14 are respectively connected to the source potential VDD and a node N2. The node N2 is connected to the source potential VSS through an N channel MOS transistor (hereinafter called “NMOS”) 15 whose drain and gate are connected so as to have a diode configuration. The bias voltage Vb is outputted through the node N2.
On the other hand, the amplifying unit 20 has an NMOS 21 of which the gate is supplied with the bias voltage Vb. The source and drain of the NMOS 21 are respectively connected to a source potential VSS and a node N3. The sources of NMOSs 22a and 22b are connected to the node N3. The drains of the NMOSs 22a and 22b are respectively connected to a source potential VDD through resistors 23a and 23b. Then, the gates of the NMOSs 22a and 22b are respectively supplied with input signals IN1 and IN2. Complementary output signals OUTn and OUTp are outputted from the drains of these NMOSs 22a and 22b. 
The operation of the differential amplifier circuit will next be explained.
Since the − input terminal of the operational amplifier 11 is supplied with the reference voltage Vref in the differential amplifier circuit, the potential of the + input terminal also reaches the reference voltage Vref in a stable state. When the potential of the node N1 (i.e., the + input terminal of the operational amplifier 11) rises for some reason here, the voltage outputted from the operational amplifier 11 also rises. Thus, the potential applied to each of the gates of the PMOSs 13 and 14 rises so that the current that flows through each of these PMOSs 13 and 14 decreases. When the current that flows through the PMOS 13 decreases, a voltage drop developed across the resistor 12 is reduced so that the potential of the node N1 is lowered. With such a feedback operation, the potential of the node N1 is controlled so as to always reach the reference voltage Vref. Thus, the current that flows through the resistor 12 results in a constant value of Vref/R12 assuming that its resistance value is R12.
The PMOSs 13 and 14 constitute the current mirror circuits respectively, and the NMOS 15 connected in series with the PMOS 14 and the NMOS 21 provided within the amplifying unit 20 are also supplied with the bias voltage Vb in common and thereby constitute current mirror circuits respectively. Thus, the current that flows through the NMOS 21 becomes a constant value of K×Vref/R12 assuming that a mirror constant is K. Since the current that flows through the NMOS 21 is equivalent to the sum of currents that flow through the resistors 23a and 23b of the amplifying unit 20 here, the minimum values of the currents that flow through the resistors 23a and 23b become 0 and the maximum values thereof become K×Vref/R12, respectively. Thus, the maximum amplitude values of the output signals OUTn and OUTp reach K×Vref×R23/R12 assuming that the resistance values of the resistors 23a and 23b are respectively R23.
Thus, even if each of the resistance values of the resistors 12, 23a and 23b is shifted from a target value due to variations in manufacturing condition, the ratio (R23/R12) between the resistance values thereof remains unchanged if these resistors 12, 23a and 23b are formed in a common manufacturing process. Therefore, the maximum amplitude values of the output signals OUTn and OUTp can be held constant.
In the differential amplifier circuit shown in FIG. 1, however, the center voltages of the output signals OUTn and OUTp fluctuate depending on the source potential VDD. Therefore, there is a fear that when the output terminals of the differential amplifier circuit are directly connected to an input unit of a circuit provided at a subsequent stage, a dc current will flow due to the difference between the center voltages. Accordingly, a problem arises in that the differential amplifier circuit must be connected via a capacitor to cut off dc components.